It is commonplace in the electronic art, particularly the semiconductor art to use multiple layers of conductors to interconnect different devices or device regions. For example, power and ground may be distributed on one layer of interconnections while signals are distributed on a different layer or, all the interconnections on a first layer may be aligned in a first direction while the interconnections on a second layer are aligned in a second direction at right angles to the first direction. Multiple conductor layers permit more compact device and circuit layouts.
The conductors are typically of metal although semiconductors and other conductive materials are also employed. As used herein the words "metal, metalization, conductor, conductive, or conducting" whether used singly or in combination with the prefix "multi-" or the words "multi-layer" are intended to refer to any conductive material, including, but not limited to metals, semiconductors, semimetals, and intermetallics.
The multiple metal layers are separated by dielectric insulating layers except at particular points where conductive vias must be provided. Often the via is merely an opening in the intervening dielectric layer through which the upper metal layer penetrates so that it locally contacts the lower metal layer. Sometimes a conductive pillar or column is provided in the via hole for interconnecting the upper and lower metal layers.
Multi-layer metal arrangements and methods are known in the semiconductor art. However, prior art arrangements and methods suffer from a number of problems and disadvantages. For example, it is important that the surfaces of the successive conductor and dielectric layers be smooth and free from cracks and steps since such features produce weak points in the overlying layers which adversely affect device yield and reliability. In order to avoid step coverage problems at the edge of via holes in the dielectric layers, the via holes in the prior art have frequently been tapered before applying the next metal layer. But, tapered via holes occupy greater device area and are therefore undesirable for high density structures.
Other problems often arise during fabrication of multi-layer metal structures due to the fact that via and conductor etching usually does not proceed with complete uniformity, that is, one location on the wafer or substrate may etch more rapidly than another. This has the result that some vias or pillars are over-etched while others are under-etched. Thus, vias which are intended to have the same width or pillars which are intended to have the same height will be of different size and those intended to be of different size may be of virtually the same size. Such problems are particularly severe when very small vias and pillars must be used or different size vias and pillars must be present on the same substrate.
An additional weakness of prior art techniques is that the first or lower metal layer is often attacked by etchants during the fabrication of the interconnecting vias and overlying metal layers. This can locally erode the first metal layer and adversely affect manufacturing yield and reliability.
Accordingly, it is an object of the present invention to provide improved means and methods for forming conductive pillars joining otherwise isolated conductor layers on planar electronic devices and circuits, particularly semiconductor integrated circuits.
It is a further object of the present invention to provide an improved means and method for conductive pillars between superposed metal layers wherein the pillars can all have the same height and predetermined lateral dimensions.
It is an additional object of the present invention to provide an improved means and method for forming conductive pillars between superposed conductor layers wherein the pillars have lateral dimensions of the same order as the thickness of the dielectric layer isolating the superposed conductors.
It is a further object of the present invention to provide the above features by a method which is insensitive to non-uniformities in etching across the wafer or other substrate.
It is an additional object of the present invention to provide conductive pillars between superposed conductor layers wherein the first conductor layer is protected from harmfull etching during formation of the conductive vias and pillars and the overlying conductor layers.